MPC8540 datasheet(900/1302 Pages) FREESCALE

900 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-78

Freescale Semiconductor

PCI/PCI-X Bus Interface

Each receiving agent must determine whether the special-cycle message is applicable to itself. It

is unnecessary to assert PCI_DEVSEL in response to a special-cycle command. The initiator of

the special-cycle transaction can insert wait states, but because there is no specific target, the

special-cycle message and optional data field are valid on the first clock PCI_IRDY is asserted.

All special-cycle transactions are terminated by master-abort; however, the master-abort bit in the

initiator’s bus status register is not set for special-cycle terminations.

16.4.2.13 PCI Error Functions

PCI provides for parity and other system errors to be detected and reported. This section describes

generation and detection of parity and error reporting for the PCI bus.

16.4.2.13.1PCI Parity

Generating parity is not optional; it must be performed by all PCI-compliant devices. All PCI

transactions, regardless of type, calculate even parity; that is, the number of ones on the

PCI_AD[31:0], PCI_C/BE[3:0], and PCI_PAR signals all sum to an even number and the number

of ones on the PCI_AD[63:33], PCI_C/BE[7:4], and PCI_PAR64 signals all sum to an even

number.

Parity provides a way to determine, on each transaction, if the initiator successfully addressed the

target and transferred valid data. The PCI_C/BE[7:4] and PCI_C/BE[3:0] signals are included in

the parity calculation to ensure that the correct bus command is performed (during the address

phase) and correct data is transferred (during the data phase). The agent responsible for driving the

bus must also drive even parity on the PAR and PCI_PAR64 signals one clock cycle after a valid

address phase or valid data transfer, as shown in Figure 16-67.

During the address and data phases, parity covers all 64 address/data signals and 8 command/byte

enable signals, regardless of whether all lines carry meaningful information. Byte lanes not

actually transferring data must contain stable (albeit meaningless) data and are included in parity

calculation. During configuration, special-cycle, or interrupt-acknowledge commands, some

address lines are not defined, but are driven to stable values and are included in parity calculation.

MPC8540 Datasheet(PDF) 900 Page - Freescale Semiconductor, Inc