MPC8540 datasheet(903/1302 Pages) FREESCALE

903 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-81

16.4.3 PCI-X Bus Protocol

The PCI-X bus protocol is an enhancement of the PCI bus protocol that features a

backward-compatible, higher-bandwidth, 32- or 64-bit multiplexed address/data bus at

frequencies up to 133 MHz. The most significant of these enhancements are the following:

•

Slightly different command types define burst and DWORD transaction types

•

A new attribute phase for each transaction provides more information about the transaction

including a byte count, sequence ID, and handling instructions (for ordering and

cacheability)

•

Restricted wait state and disconnection rules

•

A new split transaction, consisting of a split response termination and one or more split

completions, replaces the delayed transaction functionality from the PCI bus protocol.

The following sections describe the new functionality of the PCI-X bus protocol.

16.4.3.1 PCI-X Terminology

The PCI-X Addendum to the PCI Local Bus Specification introduces terminology that is helpful

when describing aspects of the protocol. This terminology is introduced in context in the following

sections. However, three terms that are important to keep in mind throughout these sections are

defined as follows:

Sequence

A sequence is one or more transactions associated with carrying out a single

logical transfer by a requester. Each transaction in the same sequence carries

the same unique sequence ID.

Requester

A requester is an initiator that first introduces a transaction into the PCI-X

domain.If a transaction is terminated with a split response, the requester

becomes the target of the subsequent split completion.

Completer

A completer is the device addressed by a transaction (other than a split

completion transaction). If a target terminates a transaction with a split

response, the completer becomes the initiator of the subsequent split

completion.

Received SERR at any phase

Rcvd SERR error

—

Detected parity error for data phase

Trgt PERR error

Detected parity error

Cache line purged

Table 16-57. PCI Mode Error Actions (continued)

PCI Error Type

Error Detect

PCI Bus Status

Comment

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