MPC8540 datasheet(905/1302 Pages) FREESCALE

905 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-83

16.4.3.3 PCI-X Attribute Phase

PCI-X defines a new attribute phase that occurs one clock cycle after the address phase. During

the attribute phase, a specially encoded attribute is driven by the initiator on PCI_C/BE[3:0] and

AD[31:0]. PCI_C/BE[3:0] provide either the upper four bits of the byte count for burst

transactions or byte enables for DWORD transactions. Figure 16-68 shows PCI_AD[31:0]

attributes for burst and DWORD transactions.

The attributes for split completion transactions are described in Section 16.4.3.6, “PCI-X Split

Transactions,” and the attributes for PCI-X configuration transactions are described in

Section 16.4.3.7, “PCI-X Configuration Transactions.”

Figure 16-68. AD[31:0] During PCI-X Burst/DWORD Attribute Phase

1100

Split-

completion

Burst/

None

Yes

(as

completer)

Yes

(as

requester)

Similar to the memory-write command, but the

transaction is associated with a previous read or

write transaction that was terminated with a split

response.

1101

Dual-address-

cycle

—

Yes

Indicates the transfer a 64-bit address (in two 32-bit

address cycles) to 64-bit addressable devices. The

actual transaction command is transfered either on

PCI_C/BE[3:0] in the second address phase for a

32-bit bus or on PCI_C/BE[7:4] for a 64-bit bus.

1110

Memory-read-

block

Burst/

None

Yes

Indicates that an initiator is requesting the transfer

of a block of data.

1111

Memory-write-

block

Burst/

None

Yes

Indicates that an initiator is transferring a block of

data.

1 Reserved command encodings are reserved for future use. The MPC8540 does not respond to these commands.

Tag

Requester Bus Number

Requester Device Number

Requester Function

Number

Lower Byte Count

(Reserved for DWORD transactions)

Table 16-58. PCI-X Command Encodings (continued)

PCI_C/

BE[3:0]

PCI -X Bus

Command

Length/

Byte-Enable

Usage

MPC8540

Supports

as Initiator

MPC8540

Supports

as Target

Definition

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