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MPC8540 Datasheet(PDF) 908 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 908 Page - Freescale Semiconductor, Inc |
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908 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 16-86 Freescale Semiconductor PCI/PCI-X Bus Interface Figure 16-70. Burst Memory Write Transaction Figure 16-71 shows a memory read block transaction. Signals preceded by “s1_” indicate a signal that is internal to the device after the signal has been sampled. Note that there are no target initial wait states for this example. Data Transfer Target’s View of the PCI Bus s1_FRAME s1_AD s1_C/BE s1_IRDY PCI_TRDY PCI_DEVSEL ADDR ATTR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 ATTR BE0 BE1 BE2 BE3 BE4 BE5 BE6 BE7 PCI Bus PCI_CLK PCI_FRAME PCI_AD PCI_C/BE PCI_IRDY PCI_TRDY 1 2 34 5 6 78 9 10 11 12 13 14 PCI_DEVSEL 15 ADDR ATTR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 ATTR BE0 BE1 BE2 BE3 BE4 BE5 BE6 BE7 CMD Decode Speed A Bus Transaction Initiator Signals Termination 2 Clocks Before End of Transaction Initiator’s View of the PCI Bus PCI_FRAME PCI_AD PCI_C/BE PCI_IRDY s1_TRDY s1_DEVSEL ADDR ATTR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 ATTR BE0 BE1 BE2 BE3 BE4 BE5 BE6 BE7 CMD CMD |
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