MPC8540 datasheet(906/1302 Pages) FREESCALE

906 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-84

Freescale Semiconductor

PCI/PCI-X Bus Interface

Table 16-59 describes the fields of the attribute for burst and DWORD transactions.

16.4.3.4 PCI-X Transactions

Figure 16-69 shows a typical PCI-X write transaction. To highlight some of the difference with the

PCI protocol, compare this to the PCI write transaction shown in Figure 16-58.

Table 16-59. Burst/DWORD Transaction Attribute Summary

Name

Description

—

Reserved. Must be 0

No snoop. This attribute indicates whether the sequence should be snooped for coherency.

0 The requester cannot guarantee that the locations between the starting and ending address,

inclusive, of this sequence are not stored in any cache in the system. Thus, all potentially

affected caches should be snooped.

1 The requester guarantees that the locations between the starting and ending address,

inclusive, of this sequence are not stored in any cache in the system. Thus, snooping is not

necessary.

Relaxed ordering. This attribute indicates whether the requester requires a transaction to be

strictly ordered. In general, devices set the RO attribute for payload sequences and clear the RO

attribute for control and status sequences. Refer to the PCI-X Addendum to the PCI Bus

Specification for a complete discussion of usage models for relaxed transaction ordering.

0 The requester requires that the transaction remain in strict order.

1 The requester guarantees that the transaction is not required to remain in strict order.

28:24

Tag

The tag attribute identifies up to 32 unique sequences from a single initiator. Tag is also a

component of the sequence ID.

23:16

Requester

Bus Number

The requester bus number attribute is supplied by the bus number field in the PCI-X status

15:11

Requester

Device

Number

The requester device number attribute is supplied by the device number field in the PCI-X status

10:8

Requester

Function

Number

The requester function number attribute is supplied by the function number field in the PCI-X

status register. The requester bus number is also a component of the sequence ID.

7:0

Lower Byte

Count

For a burst transaction attribute phase, PCI_C/BE[3:0] is concatenated with AD[7:0] to create a

12-bit byte count. The byte count indicates the number of bytes the initiator plans to transfer in the

remainder of the sequence.

For DWORD transactions, the transaction has an implicit size of up to 4-bytes. Therefore, for

DWORD transactions, there is no byte count and AD[7:0] is reserved. PCI_C/BE[3:0] contain the

individual byte enables for DWORD transactions.

MPC8540 Datasheet(PDF) 906 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 906 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL