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MPC8540 Datasheet(PDF) 910 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 910 Page - Freescale Semiconductor, Inc |
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910 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 16-88 Freescale Semiconductor PCI/PCI-X Bus Interface Figure 16-72. DWORD (4-Byte) Write Transaction Figure 16-73 shows a DWORD read transaction that can be used for a memory read DWORD or an I/O read transaction. This example has two target initial wait states before data is transfered. Figure 16-73. DWORD (4-Byte) Read Transaction 16.4.3.5 PCI-X Wait State and Termination Rules PCI-X adds the following restrictions to wait state and disconnect rules: • Initiators are not permitted to insert wait states. • Targets are not permitted to insert wait states after the initial data phase; that is, targets are only allowed to insert wait states on the initial data phase. BE = Fh PCI_CLK PCI_FRAME PCI_AD[31:0] PCI_C/BE[3:0] PCI_IRDY PCI_TRDY 12 3 4 5 6 78 9 10 PCI_DEVSEL ADDR ATTR CMD ATTR DATA0 PCI_CLK PCI_FRAME PCI_AD[31:0] PCI_C/BE[3:0] PCI_IRDY PCI_TRDY 123 4 5 6 7 89 10 11 12 PCI_DEVSEL ADDR ATTR ATTR CMD DATA0 BE = Fh |
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