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MPC8540 Datasheet(PDF) 909 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 909 Page - Freescale Semiconductor, Inc |
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909 / 1302 page  Functional Description MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 16-87 Figure 16-71. Memory Read Block Transaction Figure 16-72 shows a DWORD write transaction such as an I/O write. Note that there are no target initial wait states for this example. BE = FFh BE = FFh Target’s View of the PCI Bus s1_FRAME s1_AD s1_C/BE s1_IRDY PCI_TRDY PCI_DEVSEL ADDR ATTR ATTR PCI Bus PCI_CLK PCI_FRAME PCI_AD PCI_C/BE PCI_IRDY PCI_TRDY 1 2 34 5 6 78 9 10 11 12 13 14 PCI_DEVSEL 15 ADDR ATTR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 ATTR CMD Decode Speed A Bus Transaction Initiator Signals Termination 2 Clocks Before End of Transaction Initiator’s View of the PCI Bus PCI_FRAME PCI_AD PCI_C/BE PCI_IRDY s1_TRDY s1_DEVSEL ADDR ATTR ATTR CMD CMD PCI_AD DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 s1_AD DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 Data Transfer |
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