MPC8540 datasheet(911/1302 Pages) FREESCALE

911 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-89

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Initiators and targets can end burst transactions as follows:

— After a burst data transfer starts and the target signals it can accept more than one data

phase, the transaction can only be stopped in one of the following ways:

– Target or initiator disconnect at an allowable disconnect boundary (ADB). An ADB

is a naturally-aligned, 128-byte address; that is, an address whose lower 7 bits are

zeros.

– The transaction byte count is satisfied

– Target abort

– Burst transactions can start on any byte address. Both the initiator and the target can

disconnect on any ADB. A target is also permitted to disconnect a burst transaction

after a single data phase.

In PCI-X mode, the MPC8540 always terminates an inbound write transaction with a

target-disconnect at the ADB. Also in PCI-X mode, in addition to the target-retry conditions listed

in Section 16.4.2.8.2, “Target-Initiated Termination,” the MPC8540 may retry a subsequent

inbound transaction if a previous outbound read transaction was terminated by a master-abort, a

split-completion error message, or a target-abort.

16.4.3.6 PCI-X Split Transactions

The basic sequence for a split transaction is as follows:

1. The initiator (requester) requests the bus and the arbiter grants the bus to the requester.

2. The requester initiates a transaction (other than a split completion).

3. The target (completer) communicates its intent to split the transaction by using a split

response termination.

4. The completer requests the bus and the arbiter grants the bus to the completer

5. The completer initiates a split completion transaction. Split completions are routed back to

original requester across bridges by using requester’s bus, device and function numbers in

the split completion address.

16.4.3.6.1 Split Response

Figure 16-74 shows a split response to a read transaction. Note that the read could be either a

memory read block or a memory read DWORD transaction.

MPC8540 Datasheet(PDF) 911 Page - Freescale Semiconductor, Inc