MPC8540 datasheet(901/1302 Pages) FREESCALE

901 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-79

Figure 16-67. PCI Parity Operation

16.4.2.13.2Error Reporting

PCI provides for the detection and signaling of both parity and other system errors. Two signals

are used to report these errors—PCI_PERR and PCI_SERR. The PCI_PERR signal is used

exclusively to report data parity errors on all transactions except special cycles. The PCI_SERR

signal is used for other error signaling including address parity errors and data parity errors on

special-cycle transactions; it may also be used to signal other system errors.

Note that some errors are enabled by programming two bits—one in the PCI bus command register

and another in the PCI/X error enable register (ERR_EN). Likewise, some errors are reported in

two bits—one in the PCI bus status register and another in the PCI/X error detect register

(ERR_DR). These bits must be cleared separately; that is, clearing one does not clear the other.

For example, clearing the ERR_DR[Mstr abort error] does not clear the received master abort bit

in the PCI bus status register. In these cases, both bits must be cleared before further error reporting

can occur.

Table 16-57 shows the actions taken for each kind of error.

SYSCLK

PCI_PAR, PCI_PAR64

PCI_FRAME

PCI_AD[63:0]

ADDR

PCI_IRDY

PCI_DEVSEL

PCI_C/BE[7:0]

DATA

PCI_TRDY

PCI_PERR

PCI_SERR

CMD

DATA

ADDR

CMD

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