MPC8540 datasheet(898/1302 Pages) FREESCALE

898 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-76

Freescale Semiconductor

PCI/PCI-X Bus Interface

For PCI type 0 translations, the function number and register number fields are copied without

modification onto the PCI_AD[10:2] signals during the address phase. The PCI_AD[1:0] signals

are driven to 0b00 during the address phase for type 0 configuration cycles. The MPC8540

implements address stepping on configuration cycles so that the target’s IDSEL, which is

connected directly to one of the PCI_AD lines, reaches a stable value. This means that a valid

address and command are driven on PCI_AD[31:0] and PCI_C/BE[3:0] one clock cycle before the

assertion of PCI_FRAME.

16.4.2.11.5 Type 1 Configuration Translation

For type 1 translations, the MPC8540 copies the 30 high-order bits of the PCI CFG_ADDR

MPC8540 automatically translates PCI_AD[1:0] into 0b01 during the address phase to indicate a

type 1 configuration cycle.

16.4.2.12 Other Bus Transactions

There are two other PCI transactions that the MPC8540 supports—interrupt acknowledge and

special cycles. As an initiator, the MPC8540 may initiate both interrupt acknowledge and

special-cycle transactions; however, as a target, the MPC8540 ignores interrupt-acknowledge and

special-cycle transactions. Both transactions make use of the PCI CFG_ADDR and PCI

CFG_DATA registers described in Section 16.4.2.11.3, “PCI Configuration in Agent and Agent

Lock Modes.”

16.4.2.12.1Interrupt-Acknowledge Transactions

The PCI bus supports an interrupt-acknowledge transaction. The interrupt-acknowledge command

is a read operation implicitly addressed to the system interrupt controller. Note that the PCI

interrupt-acknowledge command does not address the MPC8540 PIC processor

interrupt-acknowledge register and does not return the interrupt vector address from the PIC unit.

See Chapter 10, “Programmable Interrupt Controller,” for more information about the PIC unit.

When the MPC8540 detects a read to PCI CFG_DATA, it checks the enable flag and the device

number in PCI CFG_ADDR. If the enable bit is set, the bus number corresponds to the local PCI

bus (bus number = 0x00), the device number is all ones (0b1_1111), the function number is all ones

(0b111), and the register number is zero (0b00_0000), then the MPC8540 performs an

interrupt-acknowledge transaction. If the bus number indicates a nonlocal PCI bus, the MPC8540

performs a type 1 configuration cycle translation, similar to any other configuration cycle for

which the bus number does not match.

The address phase contains no valid information other than the interrupt-acknowledge command

(PCI_C/BE[3:0] = 0b0000). Although there is no explicit address, PCI_AD[63:0] are driven to a

stable state, and parity is generated. Only one device (the system interrupt controller) on the PCI

bus should respond to the interrupt-acknowledge command by asserting PCI_DEVSEL. All other

MPC8540 Datasheet(PDF) 898 Page - Freescale Semiconductor, Inc