MPC8540 datasheet(895/1302 Pages) FREESCALE

895 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-73

When the MPC8540 detects an access to PCI CFG_DATA, it checks the enable flag and the device

number in the PCI CFG_ADDR register. If the enable bit is set, and the device number is not

0b1_1111, the MPC8540 performs a configuration cycle translation function and runs a

configuration-read or configuration-write transaction on the PCI bus. If the bus number

corresponds to the local PCI bus (bus number = 0x00), the MPC8540 performs a type 0

configuration cycle translation. If the bus number indicates a remote PCI bus (that is, nonlocal),

the MPC8540 performs a type 1 configuration cycle translation. The device number 0b1_1111 is

used for performing interrupt-acknowledge and special-cycle transactions. See Section 16.4.2.12,

“Other Bus Transactions,” for more information.

See Section 16.3.1.1.1, “PCI/X Configuration Address Register (CFG_ADDR),” for details on

PCI CFG_ADDR and Section 16.3.1.1.2, “PCI/X Configuration Data Register (CFG_DATA),”

for details on PCI CFG_DATA.

Note that because all PCI/X registers are intrinsically little-endian, in the following examples, the

data in the configuration register is shown in little-endian order. PowerPC processor accesses to

the PCI CFG_DATA register should use the load/store with byte-reversed instructions. External

PCI masters that use the local address map to access configuration space do not need to reverse

bytes since byte lane redirection from the little-endian PCI bus is performed internally.

Example: Configuration sequence, 4-byte data read from the revision ID/standard programming

interface/subclass code/class code registers at address offset 0x08 of the PCI/X configuration

header (device 0 on the PCI/X bus 0 is the MPC8540 itself).

Initial values:

r0 contains 0x8000_0008

r1 contains CCSRBAR + 0x0_8000 (Address of PCI CFG_ADDR register)

r2 contains CCSRBAR + 0x0_8004 (Address of PCI CFG_DATA register)

r3 contains 0xFFFF_FFFF

Code sequence:

stw r0, 0 (r1)

lwbrx r3, 0 (r2)

Results:

Address CCSRBAR + 0x0_8000 contains 0x8000_0008

Example: Configuration sequence, 4-byte data write to PCI/X register at address offset 0x14 of

Device 1 on PCI/X bus 0.

Initial values:

r0 contains 0x8000_0814

r1 contains CCSRBAR + 0x0_8000 (Address of PCI CFG_ADDR register)

r2 contains CCSRBAR + 0x0_8004 (Address of PCI CFG_DATA register)

r3 contains 0x1122_3344

MPC8540 Datasheet(PDF) 895 Page - Freescale Semiconductor, Inc