MPC8540 datasheet(894/1302 Pages) FREESCALE

894 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-72

Freescale Semiconductor

PCI/PCI-X Bus Interface

16.4.2.11.2 Accessing the PCI Configuration Space in Host Mode

To access the configuration space, a 32-bit value must be written to the PCI CFG_ADDR register

that specifies the target PCI bus, the target device on that bus, and the configuration register to be

accessed within that device. Note that the Bus Master bit in the MPC8540’s PCI bus command

0 is the MPC8540 itself; thus, device 0, bus 0 is used to access the internal PCI/X configuration

header.

Table 16-54. PCI Configuration Space Header Summary

Offset

Description

0x00

Vendor ID

Identifies the manufacturer of the device (assigned by the PCI SIG

(special-interest group) to ensure uniqueness).

0x02

Device ID

Identifies the particular device (assigned by the vendor).

0x04

Command

Provides coarse control over a device’s ability to generate and respond to PCI bus

cycles

0x06

Status

Records status information for PCI bus-related events

0x08

Revision ID

Specifies a device-specific revision code (assigned by vendor)

0x09

Class code

Identifies the generic function of the device and (in some cases) a specific

0x0C

Cache line size

Specifies the system cache line size in 32-bit units

0x0D

Latency timer

Specifies the value of the latency timer in PCI bus clock units for the device when

acting as an initiator

0x0E

Header type

Bits 0–6 identify the layout of bytes 0x10–0x3F; bit 7 indicates a multifunction

device. The most common header type (0x00) is shown in Figure 16-65 and in this

table.

0x0F

BIST

Optional register for control and status of built-in self test (BIST)

0x10–0x27 Base address registers Address mapping information for memory and I/O space

0x28

—

Reserved for future use

0x2C

Subsystem Vendor ID

Identifies the subsystem vendor ID (read-only for MPC8540)

0x2E

Subsystem ID

Identifies the subsystem ID (read-only for MPC8540)

0x30

Expansion ROM base

address

Base address and size information for expansion ROM contained in an add-on

board

0x34, 0x38 —

Reserved for future use

0x3C

Interrupt line

Contains interrupt line routing information

0x3D

Interrupt pin

Indicates which interrupt pin the device (or function) uses

0x3E

Min_Gnt

Specifies the length of the device’s burst period in 0.25-µs units

0x3F

Max_Lat

Specifies how often the device needs access to the bus in 0.25-µs units

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