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MPC8540 Datasheet(PDF) 897 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 897 Page - Freescale Semiconductor, Inc |
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897 / 1302 page ![]() Functional Description MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 16-75 Figure 16-66. PCI Type 0 Configuration Translation For PCI type 0 configuration cycles, the MPC8540 translates the device number field of the PCI CFG_ADDR register into a unique IDSEL signal for up to 21 different devices. Each device connects its IDSEL input to one of the PCI_AD[31:11] signals. For PCI type 0 configuration cycles, the MPC8540 translates the device number to ADn as shown in Table 16-55. Table 16-55. PCI Type 0 Configuration—Device Number to ADn Translation Device Number ADn Used for IIDSEL Device Number ADn Used for IIDSEL Binary Decimal Binary Decimal 0b0_0000–0b0_1001 0–9 — 0b1_0101 21 AD21 0b0_1010 10 AD31 0b1_0110 22 AD22 0b0_1011 11 AD11 0b1_0111 23 AD23 0b0_1100 12 AD12 0b1_1000 24 AD24 0b0_1101 13 AD13 0b1_1001 25 AD25 0b0_1110 14 AD14 0b1_1010 26 AD26 0b0_1111 15 AD15 0b1_1011 27 AD27 0b1_0000 16 AD16 0b1_1100 28 AD28 0b1_0001 17 AD17 0b1_1101 29 AD29 0b1_0010 18 AD18 0b1_1110 30 AD30 0b1_0011 19 AD19 0b1_1111 1 31 — 0b1_0100 20 AD20 1A device number of all ones indicates a PCI special-cycle or interrupt-acknowledge transaction. 0 1 7 8 15 16 20 21 23 24 29 30 31 Bus Number 000_0000 Reserved Device Number Function Number Register Number E 00 31 11 10 2 1 0 IDSEL–Only One Signal High Function/Register Number 00 Contents of PCI CFG_ADDR Register PCI_AD[31:0] Signals During Address Phase See Table 16-55 |
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