MPC8540 datasheet(888/1302 Pages) FREESCALE

888 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-66

Freescale Semiconductor

PCI/PCI-X Bus Interface

There are three types of target-initiated termination:

•

Disconnect—Refers to termination requested because the target is temporarily unable to

continue bursting. Disconnect implies that some data has been transferred. The initiator

may restart the transaction at a later time starting with the address of the next untransferred

data. (That is, data transfer may resume where it left off.)

•

Retry—Refers to termination requested because the target is currently in a state where it is

unable to process the transaction. Retry implies that no data was transferred. The initiator

may start the entire transaction over again at a later time. Note that the PCI Local Bus

Specification, Rev. 2.2 requires that all retried transactions must be completed.

•

Target-Abort—An abnormal case of target-initiated termination. Target-abort is used when

a fatal error has occurred or when a target can never respond.

As a target, the MPC8540 terminates a transaction with a target disconnect due to the following:

•

It cannot respond within eight PCI clock cycles (not including the first data phase).

•

The transaction is attempting to cross a 4-Kbyte boundary.

•

A single beat of data has been transferred and the inbound ATMU is marked

non-prefetchable.

•

The end of a cache line has been transferred for a cache-wrap mode write transaction. See

Section 16.4.2.3.1, “Memory Space Addressing.”

As a target, the MPC8540 responds to a transaction with a retry due to the following:

•

The 16-clock latency timer has expired, and the first data phase has not begun.

•

There is no more internal buffer space available for an inbound transaction.

Target-abort is indicated by asserting PCI_STOP and negating PCI_DEVSEL. This indicates that

the target requires termination of the transaction and does not want the transaction retried. If a

transaction is terminated by target-abort, the received target-abort bit (bit 12) of the initiator’s bus

status register and the signaled target-abort bit (bit 11) of the target’s bus status register are set.

Note that any data transferred in a target-aborted transaction may be corrupt.

For PCI writes to local memory, if an address parity error or data parity error occurs, the MPC8540

aborts the transaction internally, but continues the transaction on the PCI bus.

MPC8540 Datasheet(PDF) 888 Page - Freescale Semiconductor, Inc