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MPC8540 Datasheet(PDF) 886 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 886 Page - Freescale Semiconductor, Inc |
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886 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 16-64 Freescale Semiconductor PCI/PCI-X Bus Interface drive the PCI_C/BE[7:0] signals, even if the initiator is not ready to provide valid data (PCI_IRDY negated). Figure 16-57 illustrates a PCI single-beat write transaction. Figure 16-57. PCI Single-Beat Write Transaction Figure 16-58 illustrates a PCI burst write transaction. Figure 16-58. PCI Burst Write Transaction 16.4.2.8 Transaction Termination A PCI transaction may be terminated by either the initiator or the target. The initiator is ultimately responsible for concluding all transactions, regardless of the cause of the termination. All SYSCLK PCI_FRAME PCI_IRDY PCI_AD[63:0] ADDR PCI_DEVSEL PCI_TRDY PCI_C/BE[7:0] DATA CMD BE SYSCLK PCI_FRAME PCI_IRDY PCI_AD[63:0] ADDR PCI_DEVSEL PCI_TRDY PCI_C/BE[7:0] DATA4 DATA1 DATA2 DATA3 BE1 BE2 CMD BE4 BE3 |
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