MPC8540 datasheet(882/1302 Pages) FREESCALE

882 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-60

Freescale Semiconductor

PCI/PCI-X Bus Interface

For cache wrap mode (PCI_AD[1:0] = 0b10) reads, the critical memory address is decoded using

PCI_AD[63:2]. The address is incremented by 4 bytes after each data phase completes until the

end of the cache line is reached. For cache-wrap reads, the address wraps to the beginning of the

current cache line and continues incrementing until the entire cache line (32 bytes) is read. The

MPC8540 does not support cache-wrap write operations and executes a target disconnect after the

data phase for the end of the cache line completes for writes with PCI_AD[1:0] = 0b10. That is,

the MPC8540 does not wrap back to the beginning of the cache line. Note that the two low-order

bits on the address bus are included in all parity calculations.

16.4.2.3.2 I/O Space Addressing

For PCI I/O accesses, 32 address signals (PCI_AD[31:0]) are used to provide a byte address. After

a target has claimed an I/O access, it must determine if it can complete the entire access as

indicated by the byte enable signals. If all the selected bytes are not in the address range of the

target, the entire access cannot complete. In this case, the target does not transfer any data and

terminates the transaction with a target-abort error. See Section 16.4.2.8.2, “Target-Initiated

Termination,” for more information.

16.4.2.3.3 Configuration Space Addressing

PCI supports two types of configuration accesses that use different formats for the PCI_AD[31:0]

signals during the address phase. The two low-order bits of the address indicate the format used

for the configuration address phase—type 0 (PCI_AD[1:0] = 0b00) or type 1

(PCI_AD[1:0] = 0b01). Both address formats identify a specific device and a specific

configuration register for that device. See Section 16.4.2.11, “Configuration Cycles,” for

descriptions of the two formats.

16.4.2.4 Device Selection

The PCI_DEVSEL signal is driven by the target of the current transaction. PCI_DEVSEL

indicates to the other devices on the PCI bus that the target has decoded the address and claimed

the transaction. PCI_DEVSEL may be driven one, two, or three clock cycles (fast, medium, or

slow device select timing) following the address phase. Device select timing is encoded into the

device’s PCI bus status register. If no agent asserts PCI_DEVSEL within three clock cycles of

PCI_FRAME, the agent responsible for subtractive decoding may claim the transaction by

asserting PCI_DEVSEL.

A target must assert PCI_DEVSEL (claim the transaction) before or coincident with any other

target response (assert PCI_TRDY, PCI_STOP, or data signals). In all cases except target-abort,

once a target asserts PCI_DEVSEL, it must not negate PCI_DEVSEL until PCI_FRAME is

negated (with PCI_IRDY asserted) and the last data phase has completed. For normal termination,

negation of PCI_DEVSEL coincides with the negation of PCI_TRDY or PCI_STOP.

MPC8540 Datasheet(PDF) 882 Page - Freescale Semiconductor, Inc