MPC8540 datasheet(879/1302 Pages) FREESCALE

879 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-57

All signals are sampled on the rising edge of the PCI bus clock (SYSCLK). Each signal has a setup

and hold aperture with respect to the rising clock edge in which transitions are not allowed.

Outside this aperture, signal values or transitions have no significance. See the MPC8540

Integrated Processor Hardware Specifications for specific setup and hold times.

16.4.2.1 Basic Transfer Control

The basic PCI bus transfer mechanism is a burst, composed of an address phase followed by one

or more data phases. Fundamentally, all PCI data transfers are controlled by three

signals—PCI_FRAME (frame), PCI_IRDY (initiator ready), and PCI_TRDY (target ready). An

initiator asserts PCI_FRAME to indicate the beginning of a PCI bus transaction and negates

PCI_FRAME to indicate the end of a PCI bus transaction. An initiator negates PCI_IRDY to force

wait cycles. A target negates PCI_TRDY to force wait cycles.

The PCI bus is considered idle when both PCI_FRAME and PCI_IRDY are negated. The first

clock cycle in which PCI_FRAME is asserted indicates the beginning of the address phase. The

address and bus command code are transferred in that first cycle. The next cycle begins the first

of one or more data phases. Data is transferred between initiator and target in each cycle that both

PCI_IRDY and PCI_TRDY are asserted. Wait cycles may be inserted in a data phase by the

initiator (by negating PCI_IRDY) or by the target (by negating PCI_TRDY).

Once an initiator has asserted PCI_IRDY, it cannot change PCI_IRDY or PCI_FRAME until the

current data phase completes regardless of the state of PCI_TRDY. Once a target has asserted

PCI_TRDY or PCI_STOP, it cannot change PCI_DEVSEL, PCI_TRDY, or PCI_STOP until the

current data phase completes. In simpler terms, once an initiator or target has committed to the data

transfer, it cannot change its mind.

When the initiator intends to complete only one more data transfer (which could be immediately

after the address phase), PCI_FRAME is negated and PCI_IRDY is asserted (or kept asserted),

indicating the initiator is ready. After the target indicates the final data transfer (by asserting

PCI_TRDY), the PCI bus may return to the idle state (both PCI_FRAME and PCI_IRDY are

negated) unless a fast back-to-back transaction is in progress. In the case of a fast back-to-back

transaction, an address phase immediately follows the last data phase.

16.4.2.2 PCI Bus Commands

A PCI bus command is encoded in PCI_C/BE[3:0] during the address phase of a PCI transaction.

The bus command indicates to the target the type of transaction the initiator is requesting.

Table 16-52 describes the PCI bus commands implemented by the MPC8540.

MPC8540 Datasheet(PDF) 879 Page - Freescale Semiconductor, Inc