MPC8540 datasheet(881/1302 Pages) FREESCALE

881 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-59

16.4.2.3 Addressing

PCI defines three physical address spaces—PCI memory space, PCI I/O space, and PCI

configuration space. Access to the PCI memory and I/O space is straightforward, although one

must take into account the local memory access window and address translation being used. The

address translation registers are described in Section 16.3.1, “PCI/X Memory Mapped Registers.”

Access to the PCI configuration space is described in Section 16.4.2.11, “Configuration Cycles.”

Address decoding on the PCI bus is performed by every device for every PCI transaction. Each

agent is responsible for decoding its own address. PCI supports two types of address

decoding—positive decoding and subtractive decoding. For positive decoding, each device looks

for accesses in the address range that the device has been assigned. For subtractive decoding, one

device on the bus looks for accesses that no other device has claimed. See Section 16.4.2.4,

“Device Selection,” for information about claiming transactions.

The information contained in the two low-order address bits (PCI_AD[1:0]) varies by the address

space (memory, I/O, or configuration). Regardless of the encoding scheme, the two low-order

address bits are always included in parity calculations.

16.4.2.3.1 Memory Space Addressing

For memory accesses, PCI defines two types of burst ordering controlled by the two low-order bits

of the address—linear incrementing (PCI_AD[1:0] = 0b00) and cache wrap mode

(PCI_AD[1:0] = 0b10), as shown in Table 16-53. The other two PCI_AD[1:0] possibilities (0b01

and 0b11) are reserved. As an initiator, the MPC8540 always encodes PCI_AD[1:0] = 00 for PCI

memory space accesses. As a target, the MPC8540 executes a target disconnect after the first data

phase completes if PCI_AD[1:0] = 01 or PCI_AD[1:0] = 0b11 during the address phase of a local

memory access. See Section 16.4.2.8.2, “Target-Initiated Termination,” for more information on

target disconnect conditions.

For linear incrementing mode, the memory address is encoded/decoded using PCI_AD[63:2].

Thereafter, the address is incremented by 4 bytes after each data phase completes until the

transaction is terminated or completed (a 4-byte data width per data phase is implied). Note that

the two low-order bits on the address bus are included in all parity calculations.

Table 16-53. Supported Combinations of PCI_AD[1:0]

PCI_AD[1:0]

MPC8540 as Target

MPC8540 as Initiator

Read

Write

Read

Write

Linear

√√√√

Reserved

—

Cache Wrap

√

—

Reserved

—

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