MPC8540 datasheet(883/1302 Pages) FREESCALE

883 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-61

If the first access maps into a target’s address range, that target asserts PCI_DEVSEL to claim the

access. However, if the initiator attempts to continue the burst access across the resource boundary,

then the target must issue a target disconnect.

The MPC8540 is hardwired for fast device select timing (PCI bus status register [10–9] = 0b00).

Therefore, when the MPC8540 is the target of a transaction (local memory access or configuration

As an initiator, if the MPC8540 does not detect the assertion of PCI_DEVSEL within four clock

cycles after the address phase (that is, five clock cycles after it asserts PCI_FRAME), it terminates

the transaction with a master-abort termination; see Section 16.4.2.8.1, “Master-Initiated

Termination.”

16.4.2.5 Byte Alignment

The byte enable signals of the PCI bus (PCI_C/BE[7:0], during a data phase) are used to determine

which byte lanes carry meaningful data. The byte enable signals may enable different bytes for

each of the data phases. The byte enables are valid on the edge of the clock that starts each data

phase and stay valid for the entire data phase. Note that parity is calculated for all bytes regardless

of the state of the byte enable signals. See Section 16.4.2.13.1, “PCI Parity,” for more information.

If the MPC8540, as a target, detects no byte enables asserted, it completes the current data phase

with no permanent change. This implies that on a read transaction, the MPC8540 expects that the

data is not changed, and on a write transaction, the data is not stored.

16.4.2.6 Bus Driving and Turnaround

To avoid contention, a turnaround cycle is required on all signals that may be driven by more than

one agent. The turnaround cycle occurs at different times for different signals. The PCI_IRDY,

PCI_TRDY, PCI_DEVSEL, and PCI_STOP signals use the address phase as their turnaround

cycle. PCI_FRAME, PCI_C/BE[7:0], and PCI_AD[63:0] signals use the idle cycle between

transactions (when both PCI_FRAME and PCI_IRDY are negated) as their turnaround cycle.

PCI_PERR has a turnaround cycle on the fourth clock cycle after the last data phase.

The PCI address/data signals, PCI_AD[63:0], are driven to a stable condition during every

address/data phase. Even when the byte enables indicate that byte lanes carry meaningless data,

the signals carry stable values. Parity is calculated on all bytes regardless of the byte enables. See

Section 16.4.2.13.1, “PCI Parity,” for more information.

16.4.2.7 PCI Bus Transactions

This section provides descriptions of the PCI bus transactions. All bus transactions follow the

protocol as described in Section 16.4.2, “PCI Bus Protocol.” Read and write transactions are

MPC8540 Datasheet(PDF) 883 Page - Freescale Semiconductor, Inc