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MPC8540 Datasheet(PDF) 885 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 885 Page - Freescale Semiconductor, Inc |
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885 / 1302 page ![]() Functional Description MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 16-63 Figure 16-55 illustrates a PCI single-beat read transaction. Figure 16-55. PCI Single-Beat Read Transaction Figure 16-56 illustrates a PCI burst read transaction. Figure 16-56. PCI Burst Read Transaction 16.4.2.7.2 PCI Write Transactions This section describes PCI single-beat write transactions, and PCI burst write transactions. A PCI write transaction starts with the address phase, occurring when an initiator asserts PCI_FRAME. A write transaction is similar to a read transaction except no turnaround cycle is needed following the address phase because the initiator provides both address and data. The data phases are the same for both read and write transactions. Although not shown in the figures, the initiator must SYSCLK PCI_FRAME PCI_IRDY PCI_AD[63:0] ADDR PCI_DEVSEL PCI_TRDY PCI_C/BE[7:0] BE CMD DATA SYSCLK PCI_FRAME PCI_IRDY PCI_AD[63:0] ADDR PCI_DEVSEL PCI_TRDY PCI_C/BE[7:0] BE1 DATA2 DATA1 CMD BE2 |
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