MPC8540 datasheet(877/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-55

The grant given to a particular device may be removed and awarded to another higher-priority

device, whenever the higher-priority device asserts its request. If the bus is idle when a device

requests the bus, then the arbiter withholds the grant for 1 clock cycle. The arbiter re-evaluates the

priorities of all requesting devices and grants the bus to the highest-priority device in the following

clock cycle. This allows a turnaround clock when a higher-priority device is using address

stepping or when the bus is parked.

The low-priority group collectively has one bus transaction request slot in the high-priority group.

For N high-priority devices and M low-priority devices, each high-priority device is guaranteed at

least 1 of N+1 bus transactions and each low-priority device is guaranteed at least 1 of (N+1)

× M

bus transactions, with one low-priority device receiving the grant in 1 of N+1 bus transactions. If

all devices are programmed to the same priority level, or if the low-priority group has only one

device, the algorithm defaults to give each device an equal number of bus grants in round-robin

sequence.

For the example in Figure 16-54, assume that several devices are requesting the bus. If two masters

are in the high-priority group and three are in the low-priority group, each high-priority master is

guaranteed at least one out of three transaction slots and each low-priority master is guaranteed

one out of nine transaction slots.

In Figure 16-54, the grant sequence (with all devices, except device 4 requesting the bus and

device 3 being the current master) is 0, 2, MPC8540, 0, 2, 1, 0, 2, 3, …, and repeating. If device 2

is not requesting the bus, the grant sequence is 0, MPC8540, 0, 1, 0, 3, …, and repeating. If device

2 requests the bus when device 0 is conducting a transaction and the MPC8540 has the next grant,

the MPC8540 has its grant removed and device 2 is awarded the grant since device 2 is higher

priority than the MPC8540 when device 0 has the bus.

Figure 16-54. PCI/X Arbitration Example

Device 2

Device 0

Low-

High-Priority Group

Device 1

Device 3

Low-Priority Group

(1/3)

(1/9)

Priority

Slot

MPC8540

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