MPC8540 datasheet(876/1302 Pages) FREESCALE

876 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-54

Freescale Semiconductor

PCI/PCI-X Bus Interface

(REQ) output and grant (GNT) input signal. A simple request/grant handshake is used to gain

access to the bus. Arbitration for the bus occurs during the previous access so that no PCI/X bus

cycles are consumed due to arbitration (except when the bus is idle).

The MPC8540 provides bus arbitration logic for its master interface and up to five other external

PCI/X bus masters. The on-chip PCI/X arbiter functions in both host and agent modes, or it can

be disabled to allow for an external PCI/X arbiter.

A configuration signal (PCI_GNT2) sampled at the negation of HRESET determines if the

on-chip PCI/X arbiter is enabled (high) or disabled (low). The state of the reset signal is reflected

in bit 15 (read-only) of the PCI/X bus arbitration control register (PBACR[PAD]). Note that PAD

is the inverse of the arbiter configuration signal; that is, when PAD = 0 the arbiter is enabled, and

when PAD = 1 the arbiter is disabled. See Chapter 4, “Reset, Clocking, and Initialization,” for

more information on the reset configuration signals.

If the on-chip PCI/X arbiter is enabled, a request-grant pair of signals is provided for each external

master (PCI_REQ[0:4] and PCI_GNT[0:4]). In addition, the internal request/grant pair for the

internal master state machine of the MPC8540 governs processor, DMA, and RapidIO accesses to

the PCI/X interface. If the on-chip PCI/X arbiter is disabled, the MPC8540 uses the PCI_REQ0

signal as an output to issue its request to the external arbiter and uses the PCI_GNT0 signal as an

input to receive its grant from the external arbiter.

The following sections describe the operation of the on-chip PCI/X arbiter that arbitrates between

external PCI/X masters and the internal PCI/X bus master of the MPC8540.

16.4.1.1 PCI/X Bus Arbiter Operation

The on-chip PCI/X arbiter uses a programmable two-level, round-robin arbitration algorithm.

Each of the five external masters, plus the MPC8540, can be programmed for two priority levels,

high or low, using the appropriate bits in the PBACR. Within each priority group, the PCI/X bus

grant is asserted to the next requesting device in numerical order, with the MPC8540 positioned

before device 0.

Conceptually, the lowest-priority device is the master that is currently using the bus, and the

highest-priority device is the device that follows the current master in numerical order and group

priority. This is considered to be a fair algorithm, since a single device cannot prevent other

devices from having access to the bus; it automatically becomes the lowest-priority device as soon

as it begins to use the bus. If a master is not requesting the bus, then its transaction slot is given to

the next requesting device within its priority group.

A grant is awarded to the highest-priority requesting device as soon as the current master begins a

transaction; however, the granted device must wait until the bus is relinquished by the current

master before initiating a transaction.

MPC8540 Datasheet(PDF) 876 Page - Freescale Semiconductor, Inc