MPC8540 datasheet(874/1302 Pages) FREESCALE

874 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-52

Freescale Semiconductor

PCI/PCI-X Bus Interface

16.3.2.23 PCI-X Command Register—0x62

The 2-byte PCI-X command register is an additional standard register specified by the PCI-X

Addendum to the PCI Local Bus Specification. This register provides control over the ability to

generate and respond to PCI-X cycles. Table 16-50 describes the bits of the PCI-X command

Figure 16-52. PCI-X Command Register

16.3.2.24 PCI-X Status Register—0x64

The 4-byte PCI-X status register is an additional standard register specified by the PCI-X

Addendum to the PCI Local Bus Specification. This register is used to record additional status

information for PCI-X bus-related events. In agent mode, the device and bus number are updated

by the inbound configuration write transaction except for the inbound configuration write to

PCI-X status register. The definition of each bit is given in Table 16-51. Only 4-byte accesses to

address offset 0x64 are allowed.

Table 16-49. PCI-X Capability Pointer Register Field Description

Bits

Name

Description

7–0

Capability Pointer

Specifies the byte offset in the configuration space containing the first item in the capabilities list.

4321

000000000

MOST

MMRBC

ERO

DPRE

Reset

0000_0000_0011_0000

Offset

0x62

Table 16-50. PCI-X Command Register Field Descriptions

Bits

Name

Description

15–7

—

Reserved

6-4

MOST

Maximum outstanding split transactions (4 supported)

3-2

MMRBC Maximum memory read byte count (128 supported)

ERO

Enable relax ordering (read-only)

DPRE

Data parity error recovery enable (supported)

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