MPC8540 datasheet(834/1302 Pages) FREESCALE

834 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-12

Freescale Semiconductor

PCI/PCI-X Bus Interface

PCI_PAR64

Upper DWORD parity. The even parity bit that protects the upper 32 bits of data and upper 4 bits

of command/byte enable.

O As outputs for the bidirectional Upper DWORD Parity, these signals operate as described below.

State

Meanin

Asserted—Indicates odd parity across the PCI_AD[63:32] and PCI_C/BE[7:4] signals

during address and data phases.

Negated—Indicates even parity across the PCI_AD[63:32] and PCI_C/BE[7:4] signals

during address and data phases.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

As inputs for the bidirectional Upper DWORD Parity, these signals operate as described below.

State

Meanin

Asserted—Indicates odd parity driven by another PCI master or the PCI target during

read data phases.

Negated—Indicates even parity driven by another PCI master or the PCI target during

read data phases.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

PCI_PERR

PCI parity error

O As outputs for the bidirectional PCI parity error, these signals operate as described below.

State

Meanin

Asserted—Indicates that this PCI controller, acting as a PCI agent, detected a data parity

error. (Driven by the PCI initiator on reads; driven by the PCI target on writes.)

Negated—Indicates no error.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

As inputs for the bidirectional PCI parity error, these signals operate as described below.

State

Meanin

Asserted—Indicates that another PCI agent detected a data parity error while this PCI

controller was sourcing data (this PCI controller was acting as the PCI initiator

during a write, or was acting as the PCI target during a read).

Negated—Indicates no error.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

Note: If a parity error occurs on the last data beat of a PCI-X transaction with inbound

data (outbound read with split completion data or inbound write), the MPC8540 asserts

PERR longer than permitted by the PCI-X specification. This condition may cause a

subsequent transaction to erroneously detect a parity error. The condition may be

remedied by placing a stronger pull-up resistors on the PERR signal. For example:

• 1 Kohm for 133 MHz point-to-point operation

• 2 Kohm for 66 MHz operation

• 4 Kohm for 33 MHz operation.

These values are stronger than the specification allows (5 Kohm minimum for pull-up

resistors).

Table 16-2. PCI Interface Signals—Detailed Signal Descriptions (continued)

Signal

Description

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