| Electronic Components Datasheet Search |
|
MPC8540 Datasheet(PDF) 831 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8540 Datasheet(HTML) 831 Page - Freescale Semiconductor, Inc |
|
831 / 1302 page ![]() External Signal Descriptions MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 16-9 PCI_C/BE[7:0 ] I/ O Command/byte enable. Command encodings are described in Section 16.4.2.2, “PCI Bus Commands,” and Section 16.4.3.2, “PCI-X Command Encodings.” O As outputs for the bidirectional command/byte enable, these signals operate as described below. State Meanin g Asserted/Negated—During the address phase, PCI_C/BE[7:0] define the bus command. Byte enables determine which byte lanes carry meaningful data for PCI bus data phases. The PCI_C/BE0 signal applies to the LSB. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X Addendum Rev 1.0a I As inputs for the bidirectional command/byte enable, these signals operate as described below. State Meanin g Asserted/Negated—During the address phase, PCI_C/BE[7:0] indicate the command that another master is sending. During the PCI bus data phase, PCI_C/BE[7:0] indicate which byte lanes are valid. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X Addendum Rev 1.0a PCI_DEVSEL I/ O Device select O As outputs for the bidirectional device select, these signals operate as described below. State Meanin g Asserted—Indicates that this PCI controller has decoded the address and is the target of the current access. Negated—Indicates that this PCI controller has decoded the address and is not the target of the current access. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X Addendum Rev 1.0a I As inputs for the bidirectional device select, these signals operate as described below. State Meanin g Asserted—Indicates that some PCI agent (other than this PCI controller) has decoded its address as the target of the current access. Negated—Indicates that no PCI agent has been selected. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X Addendum Rev 1.0a Table 16-2. PCI Interface Signals—Detailed Signal Descriptions (continued) Signal I/ O Description |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |