MPC8540 datasheet(827/1302 Pages) FREESCALE

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Introduction

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-5

The following is a list of PCI-X features supported:

•

PCI-X revision 1.0a compatible

•

Support for up to 133-MHz point-to-point connection

•

Support for 32- and 64-bit interface

•

64-bit dual address cycle (DAC) support

•

On-chip arbitration with support for 5 high-priority request and grant signal pairs

•

Support for accesses to all PCI-X memory and I/O address spaces

•

Support for four split transactions

•

Complete allowable disconnect boundary (ADB) support

•

All PCI-X ordering rules enforced

•

Implementation of relaxed-ordering

•

PCI-X 3.3-V compatible

16.1.3 Modes of Operation

A number of parameters that affect the PCI/X controller modes of operation are determined at

power-on reset (POR) by reset configuration signals as described in Chapter 4, “Reset, Clocking,

and Initialization.” Table 16-1 provides a summary of these modes.

16.1.3.1 Host/Agent Modes

The PCI/X controller can function as either a PCI/X host bridge (host mode) or a peripheral device

on the PCI bus (agent mode). The PCI/X controller can also operate in agent configuration lock

mode. Note that host/agent mode selection is determined at power-up as summarized in

Section 16.5.1, “Power-On Reset Configuration Modes.”

Table 16-1. POR Parameters for PCI/X Controller

Parameter

Description

Section/Pag

Host/agent

configuration

Selects between host and agent mode for the PCI/X and RapidIO interfaces.

4.4.3.4/4-14

PCI width selection

Selects between 32-bit or 64-bit data bus width.

4.4.3.12/4-19

PCI I/O impedance

Selects the impedance of the PCI/X I/O drivers

4.4.3.13/4-19

PCI arbiter enable

Enables the on-chip PCI/X bus arbiter

4.4.3.14/4-19

PCI debug mode enable Selects between normal operation or debug mode for PCI_AD[62:58].

4.4.3.15/4-20

PCI-X configuration

Selects between PCI or PCI-X operation

4.4.3.16/4-20

PCI/X output hold

Selects the number of buffer delays for PCI output signals depending on

whether PCI or PCI-X operation is selected. This provides flexibility in meeting

minimum output hold specifications relative to SYSCLK for both PCI and PCI-X

systems

4.4.3.19/4-21

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