MPC8540 datasheet(823/1302 Pages) FREESCALE

823 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-1

Chapter 16

PCI/PCI-X Bus Interface

The MPC8540 PCI/PCI-X interface complies with the PCI Local Bus Specification, Rev. 2.2 and

the PCI-X Addendum to the PCI Local Bus Specification, Rev. 1.0a. It is beyond the scope of this

manual to document the intricacies of the PCI and PCI-X buses. This chapter describes the

PCI/PCI-X controller (referenced as PCI/X throughout this chapter) of this device and provides a

basic description of the PCI and PCI-X bus operations. The specific emphasis is directed at how

the MPC8540 implements the PCI and PCI-X buses. Designers of systems incorporating

PCI/PCI-X devices should refer to the respective specification for a thorough description of the

PCI/PCI-X buses.

NOTE

Much of the available PCI literature refers to a 16-bit quantity as a

WORD and a 32-bit quantity as a DWORD. Note that this is

inconsistent with the terminology in the rest of this manual where the

terms ‘word’ and ‘double word’ refer to a 32-bit and 64-bit quantity

respectively. Where necessary to avoid confusion, the precise number

of bits or bytes is specified.

16.1 Introduction

The PCI/X controller acts as a bridge between the PCI/X interface and the OCeaN switch fabric.

Figure 16-1 is a high-level block diagram of the PCI/X controller.

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