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MPC8540 Datasheet(PDF) 822 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 822 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
15-44
Freescale Semiconductor
DMA Controller
15.5.1.2 DMA to Ethernet
The Ethernet controllers cannot serve as DMA targets because they have no suitable internal
memory for this purpose. The Ethernet controllers have dedicated DMA channels to move data
between the external transmit and receive buffers and the internal packet buffer. This dedicated
channel is the only DMA service to the internal packet buffers.
However, Ethernet ports can serve as DMA targets by using a general-purpose DMA controller to
access the transmit and receive buffers defined by the Ethernet buffer descriptors. Because
Ethernet data buffers are located in RAM outside of the Ethernet controllers, general-purpose
DMA engines can move data to or from these memory regions. Also, because Ethernet controllers
automatically read buffer descriptors and send (or load) data buffers, a DMA transfer into (or out
of) these buffers is effectively a transfer into (or out of) the Ethernet ports.
15.5.1.3 DMA to Configuration and Control Registers
Because any internal register can be addressed with the four-channel DMA controller,
configuration and control registers throughout the device are valid DMA targets. However, the
primary purpose of DMA—to reduce processor load by moving large blocks of data— is not
served by DMA transfers of configuration data. For example, while it is possible to DMA into the
I
2C controller or programmable interrupt controller (PIC), doing so is extremely inefficient and is
seldom beneficial in normal operation. The overhead of creating DMA descriptors far exceeds any
savings in CPU cycles.
15.5.1.4 DMA to I2C
The I2C controller is not transparent to DMA transfers. Observe the caveats listed in
Section 15.5.1.3, “DMA to Configuration and Control Registers,” when accessing any I
2C
register, including the data register (I2CDR).
15.5.1.5 DMA to DUART
The DUART provides complete and sophisticated DMA support which is described in Chapter 12,
“DUART,” specifically Section 12.4.5, “FIFO Mode.”



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