MPC8540 datasheet(818/1302 Pages) FREESCALE

818 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-40

Freescale Semiconductor

DMA Controller

Figure 15-25 describes the format of the list descriptors.

Figure 15-25. List Descriptor Format

Figure 15-26 describes the format of the link descriptors.

Figure 15-26. Link Descriptor Format

15.4.5 Limitations and Restrictions

This section addresses some of the limitations and restrictions of the DMA controller and is

intended to help software maximize the DMA performance and avoid DMA programming errors.

The limitations of the DMA controller are the following:

•

Due to the limited number of buffers that the DMA controller can use, stride sizes less than

64 bytes should be avoided. Maximum utilization is obtained from strides greater than or

equal to 256-bytes. However, small stride sizes can be used for scatter-gather functions.

•

Coherent reads or writes are broken up into cache line accesses in the DMA.

Reserved

Next list descriptor address

Reserved

First link descriptor address

Source stride

Destination stride

Reserved

Offset

0x00

0x08

0x18

0x10

0x04

0x14

0x0C

0x1C

Byte count

Reserved

Source attributes

Destination attributes

Offset

0x00

0x08

0x18

0x10

0x04

Source address

Next link descriptor address

0x14

0x0C

Destination address

Reserved

0x1C

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