MPC8540 datasheet(814/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-36

Freescale Semiconductor

DMA Controller

15.4.1.6 Bandwidth Control

MRn[BWC] specifies how much data to allow a specific channel to transfer before allowing the

next channel to use the shared data transfer hardware. This promotes equitable bandwidth

allocation between channels. However, if only one channel is busy, hardware overrides the

specified bandwidth control size value. The DMA controller allows a channel to transfer up to

1 Kbyte at a time when no other channel is active.

15.4.1.7 Channel State

Table 15-21 defines the state of a channel based on the values of the channel start (MRn[CS]),

channel busy (SRn[CB]), transfer error (SRn[TE]), and channel continue (MRn[CC]) bits.

15.4.1.8 Illustration of Stride Size and Stride Distance

If operating in stride mode, the stride size defines the amount of data to transfer before jumping to

the next quantity of data as specified by the stride distance. The stride distance is added to the

current base address to point to the next quantity of data to be transferred. Figure 15-23 illustrates

the stride size and distance parameters. As shown, each time the stride distance is added to the base

address, the resulting address becomes the new base address. This sequence repeats until the

amount of data transferred equals the transfer size.

Table 15-21. Channel State Table

MRn[CS]

SRn[CB]

SRn[TE] MRn[CC]

Channel State

Idle state. This is the state of the bits out of reset.

Channel continue unexpected. Channel remains idle.

Error occurred after software halted the channel.

Channel continue unexpected. Channel remains in error halt state.

Software halted channel. The channel was busy and software cleared

MRn[CS].

Channel remains in halt state.

—

The channel has encountered an error condition and it is trying to halt.

Ready to start transfer (byte count > 0), or transfer complete (byte count = 0)

Continue transfer (only meaningful in chaining mode, not direct mode). In direct

mode, the channel continue has no effect.

Error occurred during transfer.

Channel remains in error halt state.

Transfer in progress.

Continue after reaching the end of list/link, or the first descriptor fetch after

channel continue.

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