MPC8540 datasheet(825/1302 Pages) FREESCALE

825 / 1302 page

Introduction

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-3

terminates with a disconnect before finishing the transaction. If another PCI device is granted the

PCI bus and requests a burst-read from local memory, the MPC8540, as a target, can accept the

burst-read transfer. When the MPC8540 is granted mastership of the PCI bus, the burst-write

transaction continues.

There are two blocks of memory in the design:

•

The inbound buffers

•

The outbound read buffers combined with the outbound write buffers

There are many blocks of control logic in the block. On the PCI/X side there are machines for

PCI/X controller-initiated address and data tenures for inbound and outbound data, respectively.

On the OCeaN side there are machines for fabric arbitration, outbound data, and inbound data.

As an initiator, the MPC8540 supports read and write operations to the PCI/X memory space, the

PCI/X I/O space, and the 256-byte PCI/X configuration space. As an initiator, the MPC8540 also

supports generating PCI/X special-cycle and interrupt-acknowledge transactions. As a target, the

MPC8540 supports read and write operations to local memory, and, when configured in agent

mode, read and write operations to the internal PCI/X configuration registers.

The MPC8540 can function as either a PCI/X host bridge (host mode) or a peripheral device on

the PCI/X bus (agent mode). See Section 16.1.3.1.1, “Host Mode,” for more information.

In agent mode, all of the PCI/X configuration registers in the MPC8540 can be programmed from

the PCI/X bus. See Section 16.4.2.11.3, “PCI Configuration in Agent and Agent Lock Modes,” for

more information.

The PCI/X interface provides bus arbitration for the MPC8540 and up to five other PCI/X bus

masters. The arbitration algorithm is a programmable two-level, round-robin priority selector. The

on-chip PCI/X arbiter can operate in both host and agent modes or it can be disabled to allow for

an external PCI/X arbiter.

The MPC8540 also provides an address translation mechanism to map inbound PCI/X to OCeaN

accesses and outbound OCeaN to PCI/X accesses.

16.1.1.1 MPC8540 as a PCI/X Initiator

Upon detecting an OCeaN-to-PCI/X transaction, the MPC8540 requests the use of the PCI/X bus.

For OCeaN-to-PCI/X bus write operations, the MPC8540 requests mastership of the PCI/X bus

when the source completes the write operation to the OCeaN. For OCeaN-to-PCI/X read

operations, the MPC8540 requests mastership of the PCI/X bus when it decodes that the access is

for PCI/X address space.

Once granted, the MPC8540 drives the address (PCI_AD[63:0]) and the bus command

(PCI_C/BE[7:0]) signals.

MPC8540 Datasheet(PDF) 825 Page - Freescale Semiconductor, Inc