MPC8540 datasheet(809/1302 Pages) FREESCALE

809 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-31

15.4.1.1.3 Basic Chaining Mode

In basic chaining mode, software must first build link descriptor segments in memory. Then the

current link descriptor address register must be initialized to point to the first descriptor in

memory. The DMA controller loads descriptors from memory prior to a DMA transfer. The DMA

controller begins the transfer according to the link descriptor information loaded for the segment.

After the current segment is finished, the DMA controller reads the next link descriptor from

memory and begins another DMA transfer. The transfer is finished if the current link descriptor is

the last one in memory or if an error condition occurs. The sequence of events to start and complete

a transfer in chaining mode is as follows:

1. Build link descriptor segments in memory. See Section 15.4.4, “DMA Descriptors,” for

more information on descriptors.

2. Poll the channel state (see Table 15-21), to confirm that the specific DMA channel is idle.

3. Initialize CLNDARn to point to the first link descriptor in memory.

4. Clear the mode register channel transfer mode bit, MRn[CTM], as well as MRn[XFE], to

indicate basic chaining mode. Other control parameters may also be initialized in the

mode register.

5. Clear, then set the mode register channel start bit, MRn[CS], to start the DMA transfer.

6. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.

7. SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the

last descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1),

or if an error occurs during any of the transfers.

15.4.1.1.4 Basic Chaining Single-Write Start Mode

Basic chaining single-write start mode allows a chain to be started by writing the current link

descriptor address register (CLNDARn). Setting MRn[CDSM/SWSM] in the mode register causes

MRn[CS] to be automatically set when the current link descriptor address register is written. The

sequence of events to start and complete a chain using single-write start mode is as follows:

1. Set the mode register current descriptor start mode bit, MRn[CDSM/SWSM], and the

extended features enable bit MRn[XFE]. Also, clear the channel transfer mode bit,

MRn[CTM]. This initialization indicates basic chaining and single-write start mode. Also

other control parameters may be initialized in the mode register.

2. Build link descriptor segments in memory. See Section 15.4.4, “DMA Descriptors,” for

more information on descriptors.

3. Poll the channel state (see Table 15-21), to confirm that the specific DMA channel is idle.

4. Initialize CLNDARn to point to the first descriptor segment in memory. This write

automatically causes the DMA controller to begin the link descriptor fetch and set

MRn[CS].

MPC8540 Datasheet(PDF) 809 Page - Freescale Semiconductor, Inc