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MPC8540 Datasheet(PDF) 805 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 805 Page - Freescale Semiconductor, Inc |
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805 / 1302 page ![]() Memory Map/Register Definition MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 15-27 Figure 15-21. DMA General Status Register (DGSR) Table 15-20 describes the fields of the DGSR. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TE0 0 CH0 PE0 EOLNI0 CB0 EOSI0 EOLSI0 TE1 0 CH1 PE1 EOLNI1 CB1 EOSI1 EOLSI1 W Reset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TE2 0 CH2 PE2 EOLNI2 CB2 EOSI2 EOLSI2 TE3 0 CH3 PE3 EOLNI3 CB3 EOSI3 EOLSI3 W Reset 0000_0000_0000_0000 Offset 0x2_1300 Table 15-20. DGSR Field Descriptions Bits Name Description 0 TE0 Transfer error, Channel 0 0 Normal operation 1 An error condition occurred during the DMA transfer. 1— Reserved 2 CH0 Channel halted, Channel 0 3 PE0 Programming error, Channel 0 4 EOLNI0 End-of-links interrupt, Channel 0 5 CB0 Channel busy, Channel 0 6 EOSI0 End-of-segment interrupt, Channel 0 7 EOLSI0 End-of-lists/direct interrupt, Channel 0 8 TE1 Transfer error, Channel 1 0 Normal operation 1 An error condition occurred during the DMA transfer. 9— Reserved 10 CH1 Channel halted, Channel 1 11 PE1 Programming error, Channel 1 12 EOLNI1 End-of-links interrupt, Channel 1 13 CB1 Channel busy, Channel 1 14 EOSI1 End-of-segment interrupt, Channel 1 15 EOLSI1 End-of-lists/direct interrupt, Channel 1 |
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