MPC8540 datasheet(802/1302 Pages) FREESCALE

802 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-24

Freescale Semiconductor

DMA Controller

15.3.2.10 Current List Descriptor Address Registers (CLSDARn)

The current list descriptor address registers, shown in Figure 15-17, contain the current address of

the list descriptor in memory in extended chaining mode.

In extended chaining mode, software must initialize CLSDARn to point to the first list descriptor

in memory. After finishing the last link descriptor in the current list, the DMA controller loads the

contents of the next list descriptor address register into the current list descriptor address register.

If NLSDARn[EOLSD] in the next list descriptor address register is clear, the DMA controller

reads the new current list descriptor from memory to process that list. If EOLSD in the next list

descriptor address register is set and the last link in the current list is finished all DMA transfers

are complete.

Figure 15-17. Current List Descriptor Address Registers (CLSDARn)

Table 15-16 describes the fields of the CLSDARn.

NDEOSIE

Next descriptor end-of-segment interrupt enable

0 Do not generate an interrupt if the current DMA transfer for the current descriptor is finished.

1 Generate an interrupt if the current DMA transfer for the current descriptor is finished.

29–30

—

Reserved

EOLND

End-of-links descriptor. This bit is ignored in direct mode.

0 This descriptor is not the last link descriptor in memory for this list.

1 This descriptor is the last link descriptor in memory for this list. If this bit is set, the DMA

controller advances to the next list descriptor in memory if NLSDARn[EOLSD] is also set in

extended mode.

26 27

CLSDA

000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_1134, 0x2_11B4, 0x2_1234, 0x2_12B4

Table 15-16. CLSDARn Field Descriptions

Bits

Name

Description

0–26

CLSDA

Current list descriptor address. Contains the current list descriptor address of the buffer descriptor

in memory in extended chaining mode. The descriptor must be aligned to a 32-byte boundary.

27–31

—

Reserved

Table 15-15. NLNDARn Field Descriptions (continued)

Bits

Name

Description

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