MPC8540 datasheet(801/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-23

15.3.2.8 Byte Count Registers (BCRn)

The byte count register, shown in Figure 15-15, contains the number of bytes to transfer.

Figure 15-15. Byte Count Registers (BCRn)

Table 15-14 describes the fields of the BCRn.

15.3.2.9 Next Link Descriptor Address Registers (NLNDARn)

The next link descriptor address registers, shown in Figure 15-16, contain the address for the next

link descriptor in memory. Contents transferred to the current descriptor address registers become

effective for the current transfer in basic and extended chaining modes.

Figure 15-16. Next Link Descriptor Address Registers (NLNDARn)

Table 15-15 describes the fields of the NLNDARn registers.

R 0000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_1120, 0x2_11A0, 0x2_1220, 0x2_12A0

Table 15-14. BCRn Field Descriptions

Bits Name

Description

0–5

—

Reserved

6–31

Byte count. Contains the number of bytes to transfer. The value in this register is decremented after each

DMA read operation. The maximum transfer size is 226 – 1 Bytes.

29 30

NLNDA

NDEOSIE

EOLND

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_1128, 0x2_11A8, 0x2_1228, 0x2_12A8

Table 15-15. NLNDARn Field Descriptions

Bits

Name

Description

0–26

NLNDA

Next link descriptor address. Contains the next link descriptor address in memory. The descriptor

must be aligned to a 32-byte boundary.

—

Reserved

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