MPC8540 datasheet(800/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-22

Freescale Semiconductor

DMA Controller

Table 15-12 describes the field of the DARn.

15.3.2.7.1 Destination Address Registers for RapidIO Maintenance Writes

(DARn)

If RapidIO is the destination of a transaction, the DARn registers are redefined as shown below.

Several options exist for the transaction type that can be specified. There are a number of

noncoherent write and flush types for address-based write transactions, and message types for

port-based write transactions.

Maintenance packets have an offset instead of an address. Figure 15-14 shows the DARn.

Figure 15-14. Destination Address Registers for RapidIO Maintenance Writes (DARn)

Table 15-13 describes the fields of the DARn.

Table 15-12. DARn Field Descriptions

Bits

Name

Description

0–31

DAD

Destination address. This register contains the destination address of the DMA transfer. The contents

are updated after every DMA write operation unless the final stride of a striding operation is less than

the stride size, in which case it remains equal to the address from which the last stride began.

29 30 31

HOP_COUNT

CONFIG_OFFSET

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_111C, 0x2_119C, 0x2_121C, 0x2_129C

Table 15-13. DARn Field Descriptions

Bits

Name

Description

0–7

HOP_COUNT

Maintenance packet hop count as defined by the RapidIO Interconnect Specification 1.2

8–29

CONFIG_OFFSET

Maintenance packet word offset as defined by the RapidIO Interconnect Specification 1.2

30–31

—

Reserved

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