MPC8540 datasheet(797/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-19

15.3.2.5.1 Source Address Registers for RapidIO Maintenance Reads

(SARn)

If RapidIO is the source of a transaction, the SARn registers are redefined as shown below. Several

options exist for the packet type that can be specified. A maintenance read is one of many possible

reads. Maintenance packets have an offset instead of an address. Figure 15-11 describes the SARn.

Figure 15-11. Source Address Registers for RapidIO Maintenance Reads (SARn)

Table 15-10 describes the fields of the SARn.

15.3.2.6 Destination Attributes Registers (DATRn)

The destination attributes registers, shown in Figure 15-12, contain the transaction attributes for

the DMA operation. Stride mode is enabled by setting DATRn[DSME]. Destination write

transaction type is specified using the DWRITETTYPE field.

ATMU bypass mode, which is applicable only for accesses to RapidIO, is enabled by setting

DATRn[DBPATMU]. If DBPATMU is set, DTRANSINT must be set to RapidIO and attributes

that would otherwise come from the ATMU must be specified in this register.

If DBPATMU is zero, the target interface is derived from the local access ATMU mapping and the

transaction is obtained from the value specified in DWRITETTYPE using the local address space

category.

Table 15-9. SARn Field Descriptions

Bits

Name

Description

0–31

SAD

Source address. This register contains the source address of the DMA transfer. The contents are

updated after every DMA write operation unless the final stride of a striding operation is less than the

stride size, in which case it remains equal to the address from which the last stride began.

29 30 31

HOP_COUNT

CONFIG_OFFSET

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_1114, 0x2_1194, 0x2_1214, 0x2_1294

Table 15-10. SARn Field Descriptions

Bits

Name

Description

0–7

HOP_COUNT

Maintenance packet hop_count as defined by the RapidIO Interconnect Specification 1.2

8–29

CONFIG_OFFSET Maintenance packet word offset as defined by the RapidIO Interconnect Specification 1.2

30–31

—

Reserved

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