MPC8540 datasheet(798/1302 Pages) FREESCALE

798 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-20

Freescale Semiconductor

DMA Controller

Figure 15-12. Destination Attributes Registers (DATRn)

Table 15-11 describes the fields of the DATRn.

DBPATMU

DTFLOWLVL

DPCI_ORDER DSME

DTRANSINT

DWRITETTYPE

Reset

0000_0000_0000_0000

EDAD

Reset

0000_0000_0000_0000

Offset

0x2_1118, 0x2_1198, 0x2_1218, 0x2_1298

Table 15-11. DATRn Field Descriptions

Bits

Name

Description

0–1

—

Reserved

DBPATMU

Bypass ATMU for this DMA operation

0 Route the operation through the ATMU outbound windows. DATRn[DWRITETTYPE]

should specify a local address space transaction type.

1 Bypass ATMU. Never generate an address match. Always use the attributes in the

destination attribute registers. Route the transaction to the interface specified in the

DATRn[DTRANSINT] field. Applicable only to RapidIO interface.

3—

Reserved

4–5

DTFLOWLVL

RapidIO transaction flow level

00 Lowest priority transaction flow

01 Next highest priority transaction flow

10 Highest priority transaction flow

11 Reserved

Applicable only to RapidIO interface, while DATRn[DBPATMU] is set.

DPCI_ORDER

Follow PCI transaction ordering rules on RapidIO (elevate write priority one level over reads).

Applicable only while DATRn[DBPATMU] is set.

DSME

Destination stride mode enable

0 Stride mode disabled.

1 Stride mode enabled.

Ignored in basic mode (MRn[XFE] is cleared). Striding on the destination address can be

accomplished by setting DSME and setting the desired stride size and distance in DSRn.

8–11

DTRANSINT

DMA destination transaction interface

0000–1011 Reserved

1100 RapidIO interface

1101–1111 Reserved

Applicable only while DATRn[DBPATMU] is set.

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