MPC8540 datasheet(795/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-17

Figure 15-9. Source Attributes Registers (SATRn)

Table 15-8 describes the fields of the SATRn.

345

SBPATMU

STFLOWLVL

SPCIORDER

SSME

STRANSINT

SREADTTYPE

Reset

0000_0000_0000_0000

000

ESAD

Reset

0000_0000_0000_0000

Offset

0x2_1110, 0x2_1190, 0x2_1210, 0x2_1290

Table 15-8. SATRn Field Descriptions

Bits

Name

Description

0–1

—

Reserved

SBPATMU

Bypass ATMU for this DMA operation

0 Route the operation through the ATMU outbound windows. SATRn[SREADTTYPE] should

specify a local address space transaction type.

1 Bypass ATMU. Never generate an address match. Always use the attributes in the source

attribute registers. Route the transaction to the interface specified in SATRn[STRANSINT].

Applicable only to RapidIO interface.

3—

Reserved

4–5

STFLOWLVL

RapidIO transaction flow level

00 Lowest priority transaction flow

01 Next highest priority transaction flow

10 Highest priority level transaction flow

11 Reserved

Applicable only to RapidIO interface, while SATRn[SBPATMU] is set.

SPCIORDER

Follow PCI transaction ordering rules (elevate write priority one level over reads).

Applicable only while SATRn[SBPATMU] is set.

SSME

Source stride mode enable

0 Stride mode disabled.

1 Stride mode enabled.

Ignored in basic mode (MRn[XFE] is cleared). Striding on the source address can be

accomplished by enabling SATRn[SSME] and setting the desired stride size and distance in

the SSRn.

8–11

STRANSINT

DMA source transaction interface

0000–1011 Reserved

1100 RapidIO interface

1101–1111 Reserved

Applicable only to RapidIO interface, while SATRn[SBPATMU] is set.

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