MPC8540 datasheet(767/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-141

Perform an MII Mgmt write cycle to TBI.

Writing to MII Mgmt Control with 16-bit data intended for TBI’s AN Advertisement register,

MIIMCON[0000_0000_0000_0000_0000_0001_1010_0000]

This advertises to the Link Partner that the TBI supports PAUSE and Full Duplex mode and does not support Half

Duplex mode.

Check to see if MII Mgmt write is complete.

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the write cycle was completed.

Set up the MII Mgmt for a write cycle to TBI’s Control register (write the PHY address and Register address),

MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]

the Control register is at offset address 0x00 from the TBI’s address. (in this case 0x10)

Perform an MII Mgmt write cycle to TBI.

Writing to MII Mgmt Control with 16-bit data intended for TBI’s Control register,

MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]

This enables the TBI to restart Auto-Negotiations using the configuration set in the AN Advertisement register.

Check to see if MII Mgmt write is complete.

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the write cycle was completed.

Check to see if PHY has completed Auto-Negotiation.

Set up the MII Mgmt for a read cycle to PHY MII Mgmt register (write the PHY address and Register address),

MIIMADD[0000_0000_0000_0000_0001_0000_0000_0001]

The Phy Status control register is at address 0x1 and in this case the PHY Address is 0x10.

Perform an MII Mgmt read cycle of Status Register.

Clear MIIMCOM[Read Cycle]

Set MIIMCOM[Read Cycle]

(Uses the PHY address (2) and Register address (2) placed in MIIMADD register),

When MIIMIND[BUSY]=0,

read the MIIMSTAT register and check bit 10 (AN Done)

MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]

Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend

Ability)

Perform an MII Mgmt read cycle of AN Expansion Register.

Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0110]

Clear MIIMCOM[Read Cycle]

Set MIIMCOM[Read Cycle]

(Uses the PHY address (0x10) and Register address (6) placed in MIIMADD register),

When MIIMIND[BUSY]=0,

read the MII Mgmt AN Expansion register and check bits 13 and 14 (NP Able and Page Rx’d)

MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]

Table 14-130. TBI Mode Register Initialization Steps (continued)

MPC8540 Datasheet(PDF) 767 Page - Freescale Semiconductor, Inc

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