MPC8540 datasheet(762/1302 Pages) FREESCALE

762 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-136

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-126 describes the shared signals of the GMII interface.

Table 14-127 describes the register initializations required to reconfigure the PHY to GMII mode

following initial auto-negotiation.

Table 14-126. Shared GMII Signals

TSEC Signals

I/O

No. of

Signals

GMII Signals

I/O

No. of

Signals

Function

EC_MDIO

I/O

EC_MDIO

I/O

Management interface I/O

EC_MDC

Management interface Clock

EC_GTX_CLK125

Reference Clock

Sum3

Table 14-127. GMII Mode Register Initialization Steps

Have the TSECn_GTX_CLK configuration signal pulled low for G/MII mode.

Set Soft_Reset,

MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]

Clear Soft_Reset,

MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize MACCFG2, for GMII, Full duplex operation.

Set I/F Mode bit.

MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]

(This example has Full Duplex = 1, Preamble count = 7, PAD/CRC append = 1)

Initialize ECNTRL,

ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]

(This example has Statistics Enable = 1)

Initialize MAC Station Address,

MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]

Set station address to 02_60_8C_87_65_43, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Initialize MAC Station Address,

MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]

Set station address to 02_60_8C_87_65_43, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Assign a Physical address to the TBI so as to not conflict with the external PHY Physical address,

TBIPA[0000_0000_0000_0000_0000_0000_0000_0101]

Set to 05, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Reset the management interface,

MIIMCFG[1000_0000_0000_0000_0000_0000_0000_0000]

Setup the MII Mgmt clock speed,

MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]

Set source clock divide by 14, for example, to insure that EC_MDC clock speed is approximately 2.5 MHz.

MPC8540 Datasheet(PDF) 762 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 762 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL