MPC8540 datasheet(758/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-132

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-123 describes the shared signals of the MII interface.

Table 14-124 describes the register initializations required to reconfigure the PHY to MII mode

following initial auto-negotiation.

RxD[6]

not used

RxD[7]

not used

RX_DV

RX_ER

COL

CRS

Sum

Table 14-123. Shared MII Signals

TSEC Signals

I/O

No. of

signals

MII Signals

I/O

No. of

signals

Function

EC_MDIO

I/O

EC_MDIO

I/O

Management interface I/O

EC_MDC

Management interface Clock

EC_GTX_CLK125

not used

Reference Clock

Sum

Table 14-124. MII Mode Register Initialization Steps

Have the TSECn_GTX_CLK configuration signal pulled low for G/MII mode.

Set Soft_Reset,

MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]

Clear Soft_Reset,

MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize MACCFG2, for MII, half duplex operation.

Set I/F Mode bit,

MACCFG2[0000_0000_0000_0000_0111_0001_0000_0100]

(This example has Full Duplex = 0, Preamble count = 7, PAD/CRC append = 1)

Table 14-122. MII Interface Mode Signal Configuration (continued)

TSEC Signals

Frequency [MHz] 125

Voltage[V] 3.3/2.5

MII Interface

Frequency [MHz] 25

Voltage[V] 3.3

Signals

I/O

No. of

Signals

I/O

No. of

Signals

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