MPC8540 datasheet(754/1302 Pages) FREESCALE

754 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-128

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.6.3.2 Receive Buffer Descriptor (RxBD)

In the RxBD the user initializes the E, I, and W bits in the first word and the pointer in second

word. If the data buffer is used, the TSEC modifies the E, L, F, M, BC, MC, LG, NO, SH, CR, OV,

and TR bits and writes the length of the used portion of the buffer in the first word. The M, BC,

Offset + 0

DEF

Defer indication. Hardware updates this bit if an excessive defer condition occurs.

0 This frame was not deferred.

1 If HAFDUP[EXCESS_DEFER]=1, this frame did not have a collision before it was sent

but it was sent late because of deferring. If HAFDUP[EXCESS_DEFER]=0, this frame

was aborted and not sent.

Offset + 0

TO1

Transmit software ownership. This read/write bit may be utilized by software, as necessary.

Its state does not affect the hardware nor is it affected by the hardware.

Offset + 0

HFE/LC

Huge Frame Enable (written by user)/Late collision (written by TSEC)

Valid only while it is set in first BD and the MACCFG2[Huge Frame] is cleared. If

MACCFG2[Huge Frame] is set, this bit is ignored.

0 Truncate transmit frame if its length is greater than the MAC’s Maximum Frame Length

1 Do not truncate the transmit frame.

Late collision. Written by TSEC

0 No late collision

1 A collision occurred after 64 bytes are sent. The TSEC terminates the transmission and

updates LC.

Offset + 0

Retransmission Limit. Written by TSEC

0 Transmission before maximum retry limit is hit

1 The transmitter failed (max. retry limit + 1) attempts to successfully send a message due

to repeated collisions. The TSEC terminates the transmission and updates RL.

Offset + 0 10–13

Retry Count. Written by TSEC

0000 The frame is sent correctly the first time or if RL is set then the retry limit has been

reached

nnnn One or more attempts were needed to send the transmit frame. If this field is 15, then

15 or more retries were needed. The Ethernet controller updates RC after sending

the buffer.

Offset + 0

Underrun. Written by TSEC

0 No underrun encountered (data was retrieved from external memory in time to send a

complete frame)

1 The Ethernet controller encountered a transmitter underrun condition while sending the

associated buffer. The TSEC terminates the transmission and updates UN.

Offset + 0

TXTRUNC TX truncation. Set in the last TxBD (TxBD[L] is set) when IEVENT[BABT] occurs for the

frame

Offset + 2

0–15

Data

Length

Data length is the number of octets the TSEC transmits from this BD’s data buffer. It is never

modified by the TSEC. This field must be greater than zero.

Offset + 4

0–31

TX Data

Buffer

Pointer

The transmit buffer pointer contains the address of the associated data buffer. There are no

alignment requirements for this address.

Table 14-120. Transmit Data Buffer Descriptor (TxBD) Field Descriptions

Offset

Bits

Name

Description

MPC8540 Datasheet(PDF) 754 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 754 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL