MPC8540 datasheet(753/1302 Pages) FREESCALE

753 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-127

The TSEC clears the R bit in the first word of the BD after it finishes using the data buffer. The

transfer status bits are then updated. Additional transmit frame status can be found in statistic

counters in the MIB block. Figure 14-118 shows the TxBD.

The TxBD fields are detailed in Table 14-120.

Offset + 0 R

PAD/CRC

DEF

TO1

HFE/LC

TXTRUNC

Offset + 2

Data Length

Offset + 4

TX Data Buffer Pointer

Offset + 6

Figure 14-118. Transmit Buffer Descriptor

Table 14-120. Transmit Data Buffer Descriptor (TxBD) Field Descriptions

Offset

Bits

Name

Description

Offset + 0

Ready. Written by TSEC and user

0 The data buffer associated with this BD is not ready for transmission. The user is free to

manipulate this BD or its associated data buffer. The TSEC clears this bit after the buffer

is transmitted or after an error condition is encountered.

1 The data buffer, which is prepared for transmission by the user, was not transmitted or is

currently being transmitted. No fields of this BD may be written by the user once this bit

is set.

Offset + 0

PAD/

CRC

PAD/CRC. Padding and CRC attachment for frames. (Valid only while it is set in the first BD

and MACCFG2[PAD/CRC] is cleared.) If MACCFG2[PAD/CRC] is set, this bit is ignored.

0 Do not add padding to short frames. No CRC is appended unless TxBD[TC] is set.

1 Add PAD/CRCs to frames. PAD bytes are inserted until the length of the transmitted

frame equals 64 bytes. Unlike the MPC8260 which PADs up to MINFLR value, TSEC

PADs always up to the IEEE minimum frame length of 64 bytes. CRC is always

appended to frames.

Offset + 0

Wrap. Written by user

0 The next buffer descriptor is found in the consecutive location.

1 The next buffer descriptor is found at the location defined in TBASE.

Offset + 0

Interrupt. Written by user

0 No interrupt is generated after this buffer is serviced.

1 IEVENT[TXB] or IEVENT[TXF] are set after this buffer is serviced. These bits can cause

an interrupt if they are enabled (That is, IEVENT[TXBEN] or IEVENT[TXFEN] are set).

Offset + 0

Last in frame. Written by user

0 The buffer is not the last in the transmit frame.

1 The buffer is the last in the transmit frame.

Offset + 0

Tx CRC. Written by user. (Valid only while it is set in first BD and TxBD[PAD/CRC] is cleared

and MACCFG2[PAD/CRC] is cleared and MACCFG2[CRC EN] is cleared.) If

MACCFG2[PAD/CRC] is set or MACCFG2[CRC EN] is set, this bit is ignored.

0 End transmission immediately after the last data byte with no hardware generated CRC

appended, unless TxBD[PAD/CRC] is set.

1 Transmit the CRC sequence after the last data byte.

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