MPC8540 datasheet(749/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-123

The transmit or receive timer threshold counter is reset when a corresponding interrupt is raised

and begins counting again upon deassertion of that interrupt and once IEVENT[TXF or RXF] is

set.

14.6.2.9 Inter-Packet Gap Time

If a station must transmit, it waits until the LAN becomes silent for a specified period (inter-packet

gap). After a station begins sending, it continually checks for collisions on the LAN. If a collision

is detected, the station forces a jam signal (all ones) on its frame and stops transmitting. Collisions

usually occur close to the beginning of a packet. The station then waits a random time period

(back-off) before attempting to send again. After the back-off completes, the station waits for

silence on the LAN and then begins retransmission on the LAN. This process is called a retry. If

the packet is not successfully sent within a specified number of retries, an error is indicated.

The minimum inter-packet gap time for back-to-back transmission is 96 serial clocks. The receiver

receives back-to-back packets with this minimum spacing. In addition, after waiting a required

number of clocks (based on the back-off algorithm), the transmitter waits for carrier sense to be

negated before retransmitting the packet. Retransmission begins 36 serial clocks after carrier sense

is negated for at least 60 serial clocks.

14.6.2.10 Internal and External Loop Back

Setting MACCFG1[Loop Back] causes the MAC transmit outputs to be looped back to the MAC

receive inputs. Clearing this bit results in normal operation. This bit is cleared by default.

14.6.2.11 Error-Handling Procedure

The Ethernet controller reports frame reception and transmission error conditions using the

channel BDs, the error counters, and the IEVENT register.

Programming note: When the TSEC encounters a halt condition (TSTAT[THLT] is set), it stops

processing the frame at the current TxBD. The TSEC relies on the user to manage the buffer

descriptor pointer, TBPTR, or the buffer descriptor queue before resuming transmissions. Once the

TSEC resumes, it fetches the TxBD pointed to by TBPTR.

Table 14-117. Interrupt Coalescing Timing Threshold Ranges

TSEC Interface Format and

Frequency

Interrupt Coalescing Threshold Time

Minimum (ICTT=1)

Maximum (ICTT=65535)

10Base-T at 2.5 MHz

25.6 µs

1.678 s

100Base-T at 25 MHz

2.56 µs

167.8 ms

1000Base-T at 125 MHz

512 ns

33.55 ms

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