MPC8540 datasheet(748/1302 Pages) FREESCALE

748 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-122

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.6.2.8.2 Interrupt Coalescing By Frame Count Threshold

To avoid interrupt bandwidth congestion due to frequent, consecutive interrupts, the user may

enable and configure interrupt coalescing to deliberately group frame interrupts, reducing the total

number of interrupts raised. The number of frames received or transmitted prior to an interrupt

being raised is determined by the frame threshold field (ICFCT) in the appropriate interrupt

coalescing configuration register (RXIC or TXIC). The frame threshold field may be assigned a

value between 1 and 255. A value of 0 results in boundedly undefined behavior. Note that a value

of 1 functionally defeats the advantages of interrupt coalescing since the frame threshold is

reached with each frame received or transmitted. Once the number of frames transmitted or

received reaches the threshold limit, an interrupt is raised (if the interrupt bit of the frame buffer

descriptor(s) is set and if appropriately-enabled in the IMASK register), the threshold counter is

reset, and then continues counting frames while the interrupt is active. The threshold counter is

also reset if an interrupt is raised subject to the corresponding threshold timer.

14.6.2.8.3 Interrupt Coalescing By Timer Threshold

To avoid stale frame interrupts, the user may also assign a timer threshold, beyond which any

frame interrupts not yet raised are forced (if the interrupt bit of the frame buffer descriptor(s) is set

and if enabled in the IMASK register). The timer threshold fields of the receive and transmit

interrupt coalescing configuration registers (RXIC[ICTT] and TXIC[ICTT]) are defined in units

equivalent to 64 TSEC interface clocks. That is, one timer threshold unit is 26.5 µs, 2.56 µs, or

512 ns, corresponding to interface modes 10 Mbps, 100 Mbps, or 1 Gbps, respectively.

After transmitting a frame (with TXBD[I] set, causing IEVENT[TXF] to be set), the transmit

interrupt coalescing threshold timer begins counting. When the timer threshold has been reached

an interrupt is raised if the interrupt bit of the buffer descriptor is set and IMASK[TXFEN] is set.

After receiving a frame (with RXBD[I] set, causing IEVENT[RXF] to be set), the receive interrupt

coalescing threshold timer begins counting. When the timer threshold has been reached an

interrupt is raised if the interrupt bit of the buffer descriptor is set and IMASK[RXFEN] is set.

The interrupt coalescing timer thresholds (transmit and receive, operating independently) may be

values ranging from 1 to 65535. A value of 0 results in boundedly undefined behavior.

Table 14-117 specifies the range of possible timing thresholds subject to the interface frequency

and the value of RXIC[ICTT] or TXIC[ICTT].

MPC8540 Datasheet(PDF) 748 Page - Freescale Semiconductor, Inc