MPC8540 datasheet(745/1302 Pages) FREESCALE

745 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-119

Bit-reversing the low-order byte of the CRC value (0xBC) yields BR_CRC = 0x3D = 0b00111101

The high-order 3-bits of the new BR_CRC value are used to select which 32-bit register (of the 8)

to use. This example maps the DA to register 1.

High-order 3 bits of BR_CRC: HO_CRC = 0b001 = 1

The low-order 5 bits are used to select which bit to set in the given register (with a value of 0

setting 0x8000_0000 and 31 setting 0x0000_0001). Therefore, the example DA maps to bit 29 of

Low-order 5 bits of BR_CRC: LO_CRC = 0b11101 = 29

Therefore, GADDR1 is ORed with the value 0x0000_0004.

Additional calculated examples follow:

Example 1:

•

Destination MAC address: DA = 01005E000128

•

CRC remainder value: CRC = 0x821D6CD3

•

Bit-reversed least-significant byte of CRC value: BR_CRC = 0xCB = 0b11001011

•

High-order 3 bits of BR_CRC: HO_CRC = 0b110 = 6

•

Low-order 5 bits of BR_CRC: LO_CRC = 0b01011 = 11

•

GADDR6 = 0x0010_0000

Example 2:

•

Destination MAC address: DA = 0004F0604F10

•

CRC remainder value: CRC = 0x1F5A66B5

•

Bit-reversed least-significant byte of CRC value: BR_CRC = 0xAD = 0b10101101

•

High-order 3 bits of BR_CRC: HO_CRC = 0b101 = 5

•

Low-order 5 bits of BR_CRC: LO_CRC = 0b01101 = 13

•

GADDR5 = 0x0004_0000

14.6.2.7 Flow Control

Because collisions cannot occur in full-duplex mode, gigabit Ethernet can operate at the maximum

rate. If the rate becomes too fast for a station’s receiver, the station’s transmitter can send

flow-control frames to reduce the rate. Flow-control instructions are transferred by special frames

of minimum frame size. The length/type fields of these frames have a special value. Table 14-114

lists the flow-control frame structure.

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