MPC8540 datasheet(747/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-121

•

Clear any set halt bits in TSTAT and RSTAT registers, or DMACTRL[GTS] and

DMACTRL[GRS].

•

Continue normal execution.

14.6.2.8.1 Interrupt Coalescing

Interrupt coalescing offers the user the ability to contour the behavior of the TSEC with regard to

frame interrupts. Separate but identical mechanisms exist for handling both transmitted frames and

received frames. While interrupt coalescing is enabled a transmit or receive frame interrupt

(resulting from the interrupt bit (I) of the buffer descriptor in question and appropriately-enabled

by the IMASK register) is raised either when a counter threshold-defined number of frames is

received/transmitted or the timer threshold-defined period of time has lapsed, whichever occurs

first.

Table 14-115. Non-Error Transmit Interrupts

Interrupt

Description

Action taken by TSEC

GTSC

Graceful transmit stop complete: transmitter is put into a

pause state after completion of the frame currently being

transmitted.

None

TXC

Transmit control: Instead of the next transmit frame, a

control frame was sent.

None

TXB

Transmit buffer: A transmit buffer descriptor, that is not the

last one in the frame, was updated.

Programmable “write with response”

TxBD to memory before setting

IEVENT[TXB].

TXF

Transmit frame: A frame was transmitted and the last

transmit buffer descriptor (TxBD) of that frame was

updated.

Programmable “write with response” to

memory on the last TxBD before setting

IEVENT[TXF].

Table 14-116. Non-Error Receive Interrupts

Interrupt

Description

Action taken by TSEC

GRSC

Graceful receive stop complete: Receiver is put into a

pause state after completion of the frame currently being

received.

None

RXC

Receive control: A control frame was received. As soon as

the transmitter finishes sending the current frame, a pause

operation is performed lasting for the duration specified in

the received pause control frame and beginning when the

frame was first received.

None

RXB

Receive buffer: A receive buffer descriptor, that is not the

last one of the frame, was updated.

Programmable “write with response”

RxBD to memory before setting

IEVENT[RXB].

RXF

Receive frame: A frame was received and the last receive

buffer descriptor (RxBD) of that frame was updated.

Programmable “write with response” to

memory on the last RxBD before setting

IEVENT[RXF].

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