MPC8540 datasheet(750/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-124

Freescale Semiconductor

Three-Speed Ethernet Controllers

Transmission errors are described in Table 14-118.

Reception errors are described in Table 14-119.

Table 14-118. Transmission Errors

Error

Response

Transmitter

underrun

The controller sends 32 bits that ensure a CRC error, terminates buffer transmission, sets TxBD[UN],

closes the buffer, sets IEVENT[XFUN] and IEVENT[TXE]. The controller resumes transmission after

TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared).

Retransmission

attempts limit

expired

The controller terminates buffer transmission, sets TxBD[RL], closes the buffer, sets

IEVENT[CRL/XDA] and IEVENT[TXE]. Transmission resumes after TSTAT[THLT] is cleared (and

DMACTRL[GTS] is cleared).

Excessive

defer abort

The controller terminates buffer transmission, sets TxBD[DEF], closes the buffer, sets

IEVENT[CRC/XDA], and IEVENT[TXE]. Transmission resumes after TSTAT[THLT] is cleared.

Late collision

The controller terminates buffer transmission, sets TxBD[LC], closes the buffer, sets IEVENT[LC]

and IEVENT[TXE]. The controller resumes transmission after TSTAT[THLT] is cleared (and

DMACTRL[GTS] is cleared).

Memory Read

Error

A system bus error occurred during a DMA transaction. The controller sets IEVENT[EBERR], DMA

stops sending data to the FIFO which causes an underrun error but IEVENT[XFUN] is not set. The

TSTAT[THLT] is set. Transmits are continued once TSTAT[THLT] is cleared.

Babbling

Transmit Error

A frame is transmitted which exceeds the MAC’s Maximum Frame Length and MACCFG2[Huge

Frame] is a 0. The controller sets IEVENT[BABT] and continues without interruption.

TxBD[TXTRUNC] is set in the last TxBD (TxBD[L] is set) of the frame.

Table 14-119. Reception Errors

Error

Description

Overrun error

The Ethernet controller maintains an internal FIFO buffer for receiving data. If a receiver FIFO buffer

overrun occurs, the controller sets RxBD[OV], sets RxBD[L], closes the buffer, and sets

IEVENT[RXF], The receiver then enters hunt mode (seeking start of a new frame).

Busy error

A frame is received and discarded due to a lack of buffers. The controller sets IEVENT[BSY]. In

addition, the RSTAT[QHLT] bit is set. The halted queue resumes reception once the user clears the

RSTAT[QHLT] bit.

Non-octet error

(dribbling bits)

The Ethernet controller handles a nibble of dribbling bits if the receive frame terminates as non-octet

aligned and it checks the CRC of the frame on the last octet boundary. If there is a CRC error, the

frame non-octet aligned (RxBD[NO]) error is reported, IEVENT[RXF] is set, and the alignment error

counter increments. The TSEC relies on the statistics collector block to increment the receive

alignment error counter (RALN). If there is no CRC error, no error is reported.

CRC error

If a CRC error occurs, the controller sets RxBD[CR], closes the buffer, and sets IEVENT[RXF]. This

TSEC relies on the statistics collector block to record the event. After receiving a frame with a CRC

error, the receiver then enters hunt mode.

Memory Read

Error

A system bus error occurred during a DMA transaction. The controller sets IEVENT[EBERR] and

discards the frame. In addition the RSTAT[QHLT] bit is set. The halted queue resumes reception once

the RSTAT[QHLT] bit is cleared.

Babbling

Receive Error

A frame is received that exceeds the MAC’s maximum frame length. The controller sets

IEVENT[BABR] and continues

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