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MPC8540 Datasheet(PDF) 746 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 746 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
14-120
Freescale Semiconductor
Three-Speed Ethernet Controllers
If flow-control mode is enabled (MACCFG1[Rx_Flow] is set) and the receiver identifies a
pause-flow control frame, transmission stops for the time specified in the control frame. During
this pause, only a control frame can be sent (TCTRL[TFC_PAUSE] is set). Normal transmission
resumes after the pause timer stops counting. If another pause-control frame is received during the
pause, the period changes to the new value received.
14.6.2.8 Interrupt Handling
The following describes what usually occurs within a TSEC interrupt handler:
•
If an interrupt occurs, read IEVENT to determine interrupt sources. IEVENT bits to be
handled in this interrupt handler are normally cleared at this time.
•
Process the TxBDs to reuse them if the IEVENT[TXB or TXF] were set. If the transmit
speed is fast or the interrupt delay is long, more than one transmit buffer may have been
sent by the TSEC; thus, it is important to check more than just one TxBD during the
interrupt handler. One common practice is to process all TxBDs in the interrupt handler
until one is found with R set. See Table 14-115.
•
Obtain data from the RxBD if IEVENT[RXC,RXB or RXF] is set. If the receive speed is
fast or the interrupt delay is long, the TSEC may have received more than one RxBD; thus,
it is important to check more than just one RxBD during interrupt handling. Typically, all
RxBDs in the interrupt handler are processed until one is found with E set. Because the
TSEC pre-fetches BDs, the BD table must be big enough so that there is always another
empty BD to pre-fetch. See Table 14-116.
Table 14-114. Flow Control Frame Structure
Size
[Octets]
Description
Value
Comment
7
Preamble
1
SFD
Start frame delimiter
6
Destination address
01-80C2-00-00-01 Multicast address reserved for use in MAC frames
6
Source address
2
Length/type
88-08
Control frame type
2
MAC opcode
00-01
Pause command
2
MAC parameter
Pause time as defined by the PTV[PT] field. The pause period is
measured in pause_quanta, a speed-independent constant of 512
bit-times (unlike slot time). The most-significant octet is sent first.
2
Extended MAC
parameter
Extended pause control parameter as defined by the PTV[PTE]
field. The most-significant octet is sent first.
40
Reserved
—
4
FCS
Frame check sequence (CRC)



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